UART Baud Rate Error Calculator
MCU clock and oversampling → baud divisor (AVR UBRR etc.), actual baud rate and error %, receiver tolerance by frame length, standard baud table.
Formulas
- Divisor = f ÷ (oversampling × baud) → rounded to an integer (or the register's fractional step)
- Actual baud = f ÷ (oversampling × divisor used)
- Error (%) = (actual ÷ target − 1) × 100
- AVR: BAUD = f ÷ (16 × (UBRR + 1)); double speed (U2X = 1) uses 8 × (UBRR + 1)
Why the error matters
- A UART synchronises on the falling edge of the start bit, then counts the following bits on its own clock and samples near their middle. With mismatched baud rates the sampling point drifts towards the end of the frame (parity and stop bits).
- So the tolerance shrinks as the frame gets longer. The ATmega328P datasheet gives the acceptable range as formulas by data + parity bits (D) — table below — and, assuming transmitter and receiver share the total error equally, a «recommended max receiver error» (±2.0 % at D = 8, normal speed).
- What counts is the difference between the two devices: +2 % on one side and −2 % on the other is about 4 % apart. Enter the other side's error to see the mismatch.
- Clocks that are multiples of 1.8432 MHz (11.0592, 14.7456, 18.432 MHz…) divide standard baud rates exactly — that is why datasheet table 19-11 shows 0.0 % for them.
AVR receiver range (datasheet tables 19-2 and 19-3)
| D | Normal speed, slowest ~ fastest | Recommended max receiver error | Double speed, slowest ~ fastest | Recommended max receiver error |
|---|---|---|---|---|
| 5 | 93.20 ~ 106.67 % | ±3.0 % | 94.12 ~ 105.66 % | ±2.5 % |
| 6 | 94.12 ~ 105.79 % | ±2.5 % | 94.92 ~ 104.92 % | ±2.0 % |
| 7 | 94.81 ~ 105.11 % | ±2.0 % | 95.52 ~ 104.35 % | ±1.5 % |
| 8 | 95.36 ~ 104.58 % | ±2.0 % | 96.00 ~ 103.90 % | ±1.5 % |
| 9 | 95.81 ~ 104.14 % | ±1.5 % | 96.39 ~ 103.53 % | ±1.5 % |
| 10 | 96.17 ~ 103.78 % | ±1.5 % | 96.70 ~ 103.23 % | ±1.0 % |
FAQ
Why is 115200 bps unreliable at 16 MHz?
With oversampling 16 the divisor is 8.68, rounded to 9, so the actual rate is 111,111 bps (−3.5 %). Double speed (oversampling 8) gives 17.36 → 17, 117,647 bps (+2.1 %), a smaller error.
How much error is acceptable?
It depends on the chip and frame length. The ATmega328P datasheet recommends at most ±2.0 % receiver error for 8 data bits without parity (D = 8) at normal speed. For other chips, see their receiver tolerance table.
What is a fractional divisor?
Some UARTs have a fractional part in the divisor register (e.g. 1/16 steps), which cuts the error a lot compared with integer-only dividers. How to load it depends on the chip manual.
Do USB-serial adapters have baud error too?
Yes — the adapter chip also divides its own clock. Achievable rates and errors differ by chip, so if text garbles at high baud rates, check the adapter datasheet's baud table.
For character time and the Modbus 3.5-character gap at a baud rate, use the Serial Timing Calculator.